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1 of 14 100899 features ultra- lowpower consumption, quiet, pumpless design two digitally controlled, 256-position potentiometers serial port provides means for setting and reading both potentiometers resistors can be connected in series to provide increased total resistance 20-pin tssop, 16-pin soic, and 14-pin dip packages are available. resistive elements are temperature compensated to 0.3 lsb relative linearity standard resistance values: - ds1868-10 ~ 10 k w - ds1868-50 ~ 50 k w - ds1868-100 ~ 100 k w +5v or 3v operation operating temperature range: - industrial: -40c to 85c pin assignment pin description l0, l1 - low end of resistor h0, h1 - high end of resistor w0, w1 - wiper terminal of resistor s out - stacked configuration output rst - serial port reset input dq - serial port data input clk - serial port clock input c out - cascade port output v cc - +5 volt supply gnd - ground connections nc - no internal connection v b - substrate bias voltage dnc - do not connect *all gnd pins must be connected to ground. description the ds1868 dual digital potentiometer chip consists of two digitally controlled sol id-state potentiometers. each potentiometer is composed of 256 resistive sections. between ea ch resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. the position of the ds1868 dual digital potentiometer chip www.dalsemi.com 20-pin tssop (173-mil) v b dnc h1 l1 w1 rst clk dnc dnc gnd v cc dnc dnc s out w0 h0 l0 c out dnc dq 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ds1868s 16-pin soic (300-mil) v b nc h1 l1 w1 rst clk gnd v cc nc s out w0 h0 l0 c out dq 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 14-pin dip (300-mil) v b h1 l1 w1 rst clk v cc s out w0 h0 l0 c out 14 13 12 11 10 8 1 2 3 4 5 7 dq gnd 9 6 downloaded from: http:///
ds1868 2 of 14 wiper on the resistor array is set by an 8-bit value that controls which tap point is connec ted to the wiper output. communication and control of the device is accomplished via a 3-wire serial port inte rface. this interface allows the device wiper position to be read or written. both potentiometers can be connected in series (or stacked) for an increased total re sistance with the same resolution. for multiple-device, single-processor environments, the ds1868 can be cascade d or daisy chained. this feature provides for control of multiple devices over a single 3-wire bus. the ds1868 is offered in three standard resistance values which include 10, 50, and 100 kohm versions. the part is available in 16-pin soic (300-mil), 14-pin dip, and 20-pin (173-mil) tssop package s. operation the ds1868 contains two 256-position potentiometers whose wiper positions are set by an 8-bit val ue. these two 8-bit values are written to a 17-bit i/o shift register which is used to s tore the two wiper positions and the stack select bit when the device is powered. a block diagram of the ds1868 is presented in figure 1. communication and control of the ds1868 is accomplished through a 3-wire serial port interfa ce that drives an internal control logic unit. the 3-wire serial interface consists of the three input signals: rst , clk, and dq. the rst control signal is used to enable the 3-wire serial port operation of the device. the rst signal is an active high input and is required to begin any communication to the ds1868. the clk signal input is used to provide timing synchronization for data input and output. the dq signal line is used to trans mit potentiometer wiper settings and the stack select bit configuration to the 17-bit i/ o shift register of the ds1868. figure 9(a) presents the 3-wire serial port protocol. as shown, the 3-wire port is inac tive when the rst signal input is low. communication with the ds1868 requires the transition of the rst input from a low state to a high state. once the 3-wire port has been activated, data is entered into the part on the low to high transition of the clk signal inputs. three-wire serial timing requirement s are provided in the timing diagrams of figure 9(b) ,(c). data written to the ds1868 over the 3-wire serial interface is stored in the 17-bit i/o shi ft register (see figure 2). the 17-bit i/o shift register contains both 8-bit potentiometer wiper posit ion values and the stack select bit. the composition of the i/o shift register is presented in figur e 2. bit 0 of the i/o shift register contains the stack select bit. this bit will be discussed in the secti on entitled stacked configuration. bits 1 through 8 of the i/o shift register contain the potentiometer-1 wi per position value. bit 1 will contain the msb of the wiper setting for potentiometer-1 and bit 8 the lsb for the wiper setting. bits 9 through 16 of the i/o shift register contain the value of the potentiomete r-0 wiper position with the msb for the wiper position occupying bit 9 and the lsb bit 16. downloaded from: http:///
ds1868 3 of 14 ds1868 block diagram figure 1 i/o shift register figure 2 transmission of data always begins with the stack select bit followed by the potent iometer-1 wiper position value and lastly the potentiometer-0 wiper position value. when wiper position data is to be written to the ds1868, 17 bits (or some integer multiple) of da ta should always be transmitted. transactions which do not send a complete 17 bits (or multiple) w ill leave the register incomplete and possibly an error in the desired wiper positions. after a communication transaction has been completed the rst signal input should be taken to a low state to prevent any inadvertent changes to the device shift register. once rst has reached a low state, the contents of the i/o shift register are loaded into the respective multiplexe rs for setting wiper position. a new wiper position will only engage after a rst transition to the inactive state. on device power-up, wiper position will be random. stacked configuration the potentiometers of the ds1868 can be connected in series as shown in figure 3. this is refe rred to as the stacked configuration and allows the user to double the total end-to-end resistance of t he part. the resolution of the combined potentiometers will remain the same as a single potentiom eter but with a total of 512 wiper positions available. device resolution is defined as r tot /256 (per potentiometer) ; where r tot equals the total potentiometer resistance. the wiper output for the combined stacked potentiometer will be taken at the s out pin, which is the multiplexed output of the wiper of potentiometer-0 (w0) or potentiometer-1 (w1). the potenti ometer wiper selected at the s out output is governed by the setting of the stack select bit (bit 0) of the 17-bit i/o shift register. if the stack select bit has value 0, the multiplexed output, s out , will be that of the downloaded from: http:///
ds1868 4 of 14 potentiometer-0 wiper. if the stack select bit has value 1, the multiplexed output, s out , will be that of the potentiometer-1 wiper. downloaded from: http:///
ds1868 5 of 14 stacked configuration figure 3 cascade operation a feature of the ds1868 is the ability to control multiple devices from a single proces sor. multiple ds1868s can be linked or daisy chained as shown in figure 4. as a data bit is entered into the i/o s hift register of the ds1868 a bit will appear at the c out output after a minimum delay of 50 nanoseconds. the stack select bit of the ds1868 will always be the first out the part at the beginning of a transaction. the c out pin will always have the value of the stack select bit (b0) when rst is inactive. cascading multiple devices figure 4 the c out output of the ds1868 can be used to drive the dq input of another ds1868. when connecting multiple devices, the total number of bits transmitted is always 17 times the number of ds1868s in the daisy chain. an optional feedback resistor can be placed between the c out terminal of the last device and the first ds1868 dq, input thus allowing the controlling processor to read, as well as, write data, or c ircularly clock data through the daisy chain. the value of the feedback or isolation resistor should be in the range from 2 to 10 kohms. when reading data via the c out pin and isolation resistor, the dq line is left floating by the reading device. when rst is driven high, bit 17 is present on the c out pin, which is fed back to the input dq pin through the isolation resistor. when the clk input transitions low to high, bit 17 is loaded into t he first position of the i/o shift register and bit 16 becomes present on c out and dq of the next device. after 17 bits (or 17 times the number of ds1868s in the daisy chain), the data has shifted completely a round and back to its original position. when rst transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit i/o register. downloaded from: http:///
ds1868 6 of 14 absolute and relative linearity absolute linearity is defined as the difference between the actual measured output voltage and the expected output voltage. figure 5 presents the test circuit used to measure absolute l inearity. absolute linearity is given in terms of a minimum increment or expected output when the wiper i s moved one position. in the case of the test circuit, a minimum increment (mi) or one lsb would equal 5/256 volts. the equation for absolute linearity is given as follows: (1) absolute linearity al={ v o (actual) - v o (expected)}/mi relative linearity is a measure of error between two adjacent wiper position poi nts and is given in terms of mi by equation (2). (2) relative linearity rl={ v o (n+1) - v o (n)}/mi figure 6 is a plot of absolute linearity and relative linearity versus wiper posit ion for the ds1868 at 25 c. the specification for absolute linearity of the ds1868 is 0.75 mi typical. the specification for relative linearity of the ds1868 is 0.3 mi typical. linearity measurement configuration figure 5 downloaded from: http:///
ds1868 7 of 14 ds1868 absolute and relative linearity figure 6 typical application configurations figures 7 and 8 show two typical application configurations for the ds1868. by connecting the wi per terminal of the part to a high impedance load, the effects of the wiper resistance is minimized, since the wiper resistance can vary from 400 to 1000 ohms, depending on wiper voltage. figure 7 presents the device connected in a variable gain amplifier. the gain of the circuit on figure 7 is gi ven by the following equation: a v = n - 256 256 + where n = 0 to 255 figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. note the resistance r1 is chosen to be much greater tha n the wiper resistance to minimize its effect on circuit gain. downloaded from: http:///
ds1868 8 of 14 variable gain amplifier figure 7 fixed gain attenuator figure 8 downloaded from: http:///
ds1868 9 of 14 absolute maximum ratings* voltage on any pin relative to ground (v b =gnd) -1.0v to +7.0v voltage on any pin when v b =-3.3v -3.3v to +4.7v operating temperature -40 c to +85 c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operation sections of this specification is not implied. exposur e to absolute maximum rating conditions for extended periods of time may affect relia bility. recommended dc operating conditions (-40 c to +85 c; v cc =5.0v 10%) parameter symbol min typ max units notes supply voltage v cc 4.52.7 5.53.3 v 1 15 input logic 1 v ih 2.0 v cc +0.5 v 1, 2 input logic 0 v il -0.5 +0.8 v 1, 2 ground gnd gnd gnd v 1 resistor inputs l, h, w v b -0.5 v cc +0.5 v 2, 15 substrate bias v b -3.3 gnd v 1, 15 dc electrical characteristics (-40 c to +85 c; v cc =5.0v 10%) parameter symbol min typ max units notes supply current i cc 400 m a 12 input leakage i li -1 +1 m a wiper resistance r w 400 1000 w wiper current i w 1 ma logic 1 output @ 2.4 volts i oh -1 ma 8, 9 logic 0 output @ 0.4 volts i ol 4 ma 8, 9 standby current i stby 1 m a 14 analog resistor characteristics (-40 c to +85 c; v cc =5.0v 10%) parameter symbol min typ max units notes end-to-end resistor tolerance -20 +20 % 16 absolute linearity 0.75 lsb 4 relative linearity 0.3 lsb 5 -3 db cutoff frequency f cutoff hz 7 noise figure 11 temperature coefficient 750 ppm/c downloaded from: http:///
ds1868 10 of 14 downloaded from: http:///
ds1868 11 of 14 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf 3, 6 output capacitance c out 7 pf 3, 6 ac electrical characteristics (-40 c to +85 c; v cc =5.0v 10%) parameter symbol min typ max units notes clk frequency f clk dc 10 mhz 10 width of clk pulse t ch 50 ns 10 data setup time t dc 30 ns 10 data hold time t cdh 10 ns 10 propagation delay time low to high level clock to output t plh 50 ns 10, 13 propagation delay time high to low level t plh 50 ns 10, 13 rst high to clock input high t cc 50 ns 10 rst low from clock input high t hlt 50 ns 10 rst inactive t rlt 125 ns 10 clock low to data valid on a read t cdd 30 ns 10 clk rise time, clk fall time t cr 50 ns 10 notes: 1. all voltages are referenced to ground. 2. resistor inputs cannot exceed v b - 0.5v in the negative direction. 3. capacitance values apply at 25 c. 4. absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. device test limits 1.6 lsb. 5. relative linearity is used to determine the change in voltage between successi ve tap positions. device test limits 0.5 lsb. 6. typical values are for t a = 25 c and nominal supply voltage. 7. -3 db cutoff frequency characteristics for the ds1868 depend on potentiometer total resis tance: ds1868-010; 1 mhz, ds1868-050; 200 khz; and ds1868-100; 80 khz. 8. cout is active regardless of the state of rst . 9. v ref = 1.5 volts. 10. see figure 9(a), (b), and (c). 11. noise < -120 db/ hz . reference 1 volt (thermal). 12. supply current is dependent on clock rate (see figure 11). 13. see figure 10. 14. standby currents apply when rst , llic, dq are in the low-state. 15. when biasing the substrate minimum v b = -3.0v 10% and maximum v cc = 3.0v 10%. 16. valid at 25 c only. downloaded from: http:///
ds1868 12 of 14 timing diagrams figure 9 (a) 3-wire serial interface general overview (b) start of communication transaction (c) end of communication transaction downloaded from: http:///
ds1868 13 of 14 digital output load schematic figure 10 typical supply current vs. serial clock rate figure 11 downloaded from: http:///
ds1868 14 of 14 ds1868 20-pin tssop dim min max a mm - 1.10 a1 mm 0.05 - a2 mm 0.75 1.05 c mm 0.09 0.18 l mm 0.50 0.70 e1 mm 0.65 bsc b mm 0.18 0.30 d mm 6.40 6.90 e mm 4.40 nom g mm 0.25 ref h mm 6.25 6.55 phi 0 8 downloaded from: http:///

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